U.S. Pat. No. 6,010,948 (Yu, et al.) "A New Shallow-Trench-Isolation Process", issued Jan. 4, 2000, Assigned to the Same Assignee as the present invention.
1. Field of the Invention
The present invention relates to the manufacture of semiconductor devices and more particularly to the manufacture of shallow trench isolation (STI) features of integrated circuits.
2. Description of the Related Art
The structure and function of shallow trench isolation is well known in the art. Shallow trench isolation is commonly used to provide a very high resistance between circuit elements of an integrated circuit to effectively insulate the respective circuit elements from one another.
Shallow trench isolation is formed by selectively forming recesses or trenches 10 in the surface of the semiconductor substrate 5 as shown in FIG. 1a. The shallow trenches are filled with an insulating material such as silicon dioxide (SiO.sub.2). Traditionally, the fill layer of silicon dioxide (SiO.sub.2) is formed by chemical vapor deposition (CVD) of ozone assisted tetraethylorthosilane (03-TEOS) or a spun-on-glass (SOG) form of silicon dioxide. The fill oxide layer is planarized by chemical/mechanical planarization (CMP) or chemical etching of the silicon dioxide from the surface of the semiconductor substrate 5.
Stop layers of silicon nitride (Si.sub.x N.sub.y) 20 and silicon dioxide (SiO.sub.2) 15 are striped to form the transistors of the integrated circuits. Impurity species such as boron (B) and arsenic (As) are diffused into the surface of the semiconductor substrate adjacent to the sidewalls of the trenches 10. These diffusions form the sources and drains of the transistors of integrated circuits.
The surface of the semiconductor substrate is then etched with dilute hydrofluoric acid (HF) to remove any residual oxides prior to the formation of the contact metallurgy on the sources and drains. The dilute hydrofluoric acid will additionally reduce the thickness of the fill oxide layer in the shallow trench.
Titanium, cobalt, or titanium nitride are alloyed to the surface of the semiconductor substrate at the sources and the drains of the transistors to form a titanium salicide (TiSi.sub.x) or cobalt salicide (CoSi.sub.x). The reduced thickness of the fill oxide layer causes increased junction leakage.
Further, in p-type sources and drains, the boron (B) implant species will diffuse into the fill oxide layer in the shallow trenches. This will cause a reduction in the carrier concentration in the p-type diffusions forming the sources and drains, thus further increasing the junction leakage of the transistors.
The semiconductor substrate is further processed to complete the metalization and final back end processing to form the integrated circuit.
U.S. Pat. No. 5,112,772 (Wilson et al.) discloses a method of fabricating a trench structure. The semiconductor substrate has a silicon dioxide layer, a polysilicon layer, and a silicon nitride layer formed on its surface. A trench is formed through the silicon dioxide (SiO.sub.2) layer, the polysilicon layer, and the silicon nitride layer and into the semiconductor substrate. A dielectric liner is formed on the sidewalls of the trench, which is then filled with a trench fill material. Portions of the trench liner above the trench fill material are removed and a conformal layer is then formed on the trench structure. The conformal layer and a portion of the trench fill material are then oxidized.
U.S. Pat. No. 5,208,179 (Okazawa) teaches a method of fabricating a semiconductor integrated circuit such as a programmable read only memory (PROM) cell. The method begins with forming a first gate insulating film on a main surface of a semiconductor substrate. A first polysilicon layer, a second gate insulating film, and a second polysilicon layer are then deposited on the surface of the semiconductor substrate. Insulating trenches are then formed by selectively removing the second polysilicon layer, the second gate insulating film, the first polysilicon layer, the fast gate insulating film, and the semiconductor substrate. A borophososilicate glass (BPSG) film is formed over the entire surface filling the trenches. The BPSG film is selectively removed to leave it only in the trenches. In the prior art of Okazawa, the phosphorus and boron contained in the BPSG evaporated in response to a heat treatment used for forming the gate insulating film. Therefore, a portion of the evaporated phosphorus or boron was taken into the gate insulating film, which degraded the characteristics and the reliability of a PROM cell transistor. The invention grows the BPSG film after the first and second gate insulating film is formed. Hence, phosphorus or boron contained in the BPSG film is not taken into both of the gate insulating films.
U.S. Pat. No. 5,316,965 (Philipossian et al.) discloses an improved process for planarizing an isolation barrier in the fabrication of an integrated circuit on a semiconductor substrate. The process involves reducing the etch rate of the field oxide independently of the sacrificial oxide layer. The field oxide layer is implanted with nitrogen ions and then thermally annealed resulting in a hardened and densified field oxide. In subsequent operations, a sacrificial oxide layer is formed on the semiconductor top surface by thermal oxidation. Upon etching with hydrofluoric acid (HF), the etch rate of the hardened field oxide is significantly reduced relative to untreated field oxide. Thus, the exposed hardened field oxide is etched at about the same rate as the sacrificial oxide layer. In the example given, the etch rate of untreated densified TEOS field oxide in 10:1 HF is 6.90 .ANG./sec, while the etch rate of TEOS field oxide hardened according to the processes of this invention is 5.90 .ANG./sec. After planarization using the hardened field oxide, depressions in the isolation barrier are eliminated.
U.S. Pat. No. 5,447,884 (Fahey et al.) relates to a process for forming trench isolation in which the trench is etched in a reactive ion etching process, and lined with a thin liner nitride having a thickness &lt;5 nanometers. A feature of the invention is the use of a pyrogenic oxide anneal (wet oxidation) at a temperature of about 80.degree. C. This anneal densifies the oxide liner as is conventional, but at a much lower temperature than conventional argon annealing.
U.S. Pat. No. 5,492,858 (Bose et al.) discloses is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.